Home > About Cadence > Events > Event Details

DVCon 2014

Industry Conference  
03 Mar 2014 - 06 Mar 2014  
DoubleTree Hotel, San Jose, CA  

DVCon is the premier conference for functional design and verification, bringing you information from the leading edge of technology, techniques, standards, and methods.

Visit Cadence in booth #505 and we’ll introduce you to the latest tools, methodologies, and support you need for designing and verifying complex silicon, SoCs, and systems. Talk to our experts focused on VIP and IC/SoC/system verification. Pay attention to the press, as you may even see some very exciting new verification tools from Cadence being announced at the show!

Join us for the following show highlights: Gain real-world insight from the following technical sessions:

Session 1P: Poster Sessions – Tuesday, March 4, 10:30am-12:00pm
  • 1P.5: Checking Security Path with Cadence Incisive Enterprise Verifier IEV: New Application Development, Chris Komar of Cadence
  • 1P.10: Novel Verification Techniques for ARM A15 Multi-Core Subsystem Using IEEE 1647, Vaibhav Mahimkar, Akshit Dayal, Van Huynh, Tomas Huynh, and Erwin Hermanto of Texas Instruments, Inc.
  • 1P.11: Resetting Anytime with the Cadence UVM Reset Package, Courtney Schmitt of Analog Devices, Inc., and Phu L. Huynh, Stephanie McInnis, Uwe Simm of Cadence
  • 1P.14: Early Development of UVM Based Verification Environment of Image Signal Processing SoC’s Using TLM Reference Model of RTL, Abhishek Jain and Giuseppe Bonanno of STMicroelectronics
  • 1P.16: Verifying Multiple DUV Representations with a Single UVM-e Testbench, Matt Graham of Cadence
  • 1P.24: Connecting the Dots: Application of Formal Verification for SoC Connectivity, Bin Ju of Cadence
  • 1P.29: Metric Driven Mixed-Signal Verification Methodology and Practices for Complex Mixed-Signal ASSPs, Frank Yang, Andy Sha, and Morton Zhao of Analog Devices, Inc., Yanping Sha of Cadence Design Systems, Inc.
Session 1: System-Level Design I – Tuesday, March 4, 9:00am - 10:30am
  • 1.2: Hardware and Firmware Co-Development Using State-of-the-Art Verification Techniques in Hardware Acceleration, Joel Artmann - Medtronic, Inc.
Session 3: HW/SW Co-Verification – Tuesday, March 4, 9:00am - 10:30am
  • 3.3: Use of Software UVC to Automate and Randomize SOC Verification, Madhavi Kulkarni, Neyaz Khan, and Kara Tervooren of Maxim Integrated
Session 5: Mixed-Signal Design and Verification – Tuesday, March 4, 3:00pm - 5:00pm
  • 5.1: Automated Comparison of Analog Behavior in a UVM Environment, Sebastian Simon, Alexander E. Rath, Volkan Esen, and Wolfgang Ecker of Infineon Technologies AG
  • 5.3: Efficient SoC Level Mixed Signal Frontend Verification Using WREAL Models, Anu Marisha, Nayana Prakash, Udit Kumar,and Rajesh Tiwari of Texas Instruments India Pvt. Ltd., Vijay K. Birange of Cadence Design Systems, Inc.
Session 9: Advanced Methodologies and Testbenches II – Wednesday, March 5, 10:00am - 11:30am
  • 9.2: UVM Testbench Considerations for Acceleration, Kathleen Meade of Cadence
  • 9.3: Applying Test-Driven Development Methods To Design Verification Software In UVM-e, Doug Gibson and Michael Kontz of Hewlett-Packard Co
Session 10: Verification Process and Resource Management – Wednesday, March 5, 3:30pm - 5:00pm
  • 10.2: A Guide to Using Continuous Integration Within the Verification Environment, Jason Sprott and André Winkelmann of Verilab, Inc., Gordon McGregor of Nitero, Inc.
  • 10.3: An Assertion Based Approach to Implement VHDL Functional Coverage, Tagbo C. Ekwueme-Okoli of Cadence, Susan Eickhoff and Michael Wazlowski of IBM
Session 11: SoC and IP Integration Methods and Tools – Wednesday, March 5, 3:30pm - 5:00pm
  • 11.1: Reusing UVM Testbenches in a Cycle Simulator, Kristina Hager of IBM, Andrew Lynch and Umer Yousafzai of Cadence
  • 11.3: Accelerated, High Quality SoC Memory Map Verification Using Formal Techniques, Rajesh Kedia and Cletan Sequeira of Texas Instruments, Lokesh Babu Pundreeka and Bijitendra Mittra of Cadence
Session 12: Interoperability of Models and/or Tools – Wednesday, March 5, 3:30pm - 5:00pm
  • 12.1: Multi-Language Verification: Solutions for Real World Problems, Vitaly Yankelevich of Cadence, Bryan S. Sniderman of Advanced Micro Devices
  • 12.2: Leveraging Formal to Verify SoC Register Map, Anand Lakshmanan of Marvell Semiconductor, Jose Barandiaran of Cadence

Questions About this Event?
Send email to events@cadence.com