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DesignCon 2014

 
Type:
Industry Conference  
Date:
28 Jan 2014 - 31 Jan 2014  
Location:
Santa Clara, CA  

Taking place annually in Silicon Valley, DesignCon is the largest educational conference and technology exhibition for chip, board, and systems design engineers in the high-speed communications and semiconductor communities. Visit Cadence at booth # 507, where you’ll see demos of our Allegro® Sigrity® solutions for signal integrity and power integrity. Be the first to see features released in the latest version of ASI, including new technology supporting analysis and compliance checking of DDR4 interfaces. Demos in the Cadence® booth include:
  • Constraint-driven power Integrity design and analysis
  • Power-aware memory interface design and analysis
  • Multi-gigabit serial link design and analysis
  • Chip-package-board co-analysis
Also, don’t miss these Cadence speaker sessions:
  • Panel: System-Level Power Integrity: Tools Providers and Tool Users Engage
    • Session Code: 11-WE7
    • Cadence speaker: Brad Brim
    • Location: Ballroom G
    • Date: Wednesday, January 29
    • Time: 3:45pm-5:00pm
  • Paper: Model Extraction and Circuit Simulation Approaches for Successful SSO Analysis of Chip-Package-Board Systems
    • Session Code: 4-TH3
    • Cadence speaker: Brad Brim
    • Location: Ballroom F
    • Date: Thursday, January 30
    • Time: 10:15am-10:55am
  • Panel: Post-Equalization Metrics at 25Gbps and Beyond
    • Session Code: 8-TH7
    • Cadence speaker: Ken Willis
    • Location: Ballroom F
    • Date: Thursday, January 30
    • Time: 3:45pm-5:00pm
  • Paper: Advanced Power-Aware Buffer Behavior Model with Overclocking Solution
    • Session Code: 4-FR3
    • Cadence speaker: Joy Li
    • Location: Ballroom F
    • Date: Friday, January 31
    • Time: 10:40am-11:20am

Questions About this Event?
Send email to events@cadence.com