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Archived Webinar: Augmenting Simulation Via Low-Power Verification Methodologies with Emulation

 
Type:
Webinar  
Orignal webinar date:
11 Dec 2013  
Location:
Online  
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Join Cadence for an informative webinar on two methodologies to migrate low-power verification from simulation to emulation.

Speakers
Dieter Thuemmel - Solutions Architect, Hardware System Verification, Cadence
Joel Ake - Staff Product Engineer, Hardware System Verification, Cadence

Dynamic Power Analysis (DPA) can be instrumental in providing good power estimations at the architectural and design levels and very accurate power estimations at the implementation level. DPA can help fix any design issues prior to tapeout and prove the power awareness of complex design intellectual property (IP). DPA is required to provide the necessary measurements and enable a successful refinement approach. An automated flow and the ability to run long, real scenarios in a shorter time span that correlates power with performance are essential to power budgeting, package selection, and overall risk and cost reduction strategies.

Power shut-off (PSO) verification methodology for emulation enables you to accelerate the simultaneous verification of low-power and logical design behaviors. You can use emulation to quickly verify many different power-reducing methodologies. Common Power Format (CPF) descriptions of third-party IP or block-level designs are easily integrated into the most powerful debug tools available for emulation.

Who should attend?
  • Design and verification engineers
  • System architects and engineers
  • Test engineers
  • Firmware engineers
  • System engineers

What you will learn
  • How to compliment power analysis with emulation beyond a traditional simulation-based approach
  • How to obtain meaningful system-on-chip (SoC)-level power analysis before silicon availability
  • How to optimize power efficiency with low-power design and verification techniques with simulation acceleration
  • Methods to achieve accurate peak power analysis at block, sub-system, and system level using Dynamic Power Analysis

Questions About this Event?
Send email to webinar_info@cadence.com

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