Cadence is excited to be presenting at the ARM® Technology Symposium in Paris, France.
Measure and Optimize the System Performance of a Smartphone RTL DesignPresented by Stewart Penman, Staff Solutions Engineer, Cadence
ARM CoreLink™ system intellectual property (IP) addresses the complexity of smartphone design by managing connections of the processing subsystem, memory subsystem, and an array of peripherals. These connected systems provide high performance while minimizing the device's thermal and power profile. To harness the ability of the CoreLink IP to support a variety of peripheral combinations, the designer must analyze the configured IP under a variety of use cases to ensure that performance requirements are met. This presentation will describe a way to measure and debug the performance of designs using the ARM CoreLink 400 series. Simulations for these implementations will be run for different use cases, giving a clear picture of how design decisions affect performance and what tradeoffs yield the best options and configurations. The session will also cover a newly enhanced tool, Cadence Interconnect Workbench.
ExhibitionIn the exhibit hall, Cadence will showcase our “microcontrollers for Internet of Things” demo, which includes an ARM Cortex®-M processor. The demo will cover design, verification, and implementation of a microcontroller, including analog, digital, hardware, and software. It will include real number modeling of analog behavior for functional verification without run-time penalty. The demo will also cover low-power verification using dynamic and static methods and an integrated physical implementation flow for meeting performance and power targets in silicon. Learn more at our booth on the exhibition floor at the ARM Technology Symposium!
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