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Front-End Design Summit: Physically Aware Design

 
Type:
Cadence Event  
Date:
05 Dec 2013 (9:00am - 5:00pm PST)  
Location:
Cadence Design Systems Campus, Bldg. 10 , San Jose, CA  

Save closure time and boost performance by incorporating knowledge of physically aware design early into your front-end design implementation flow

With the adoption of advanced process nodes, design closure is becoming increasingly difficult due to the lack of convergence between the front end and the back end of the register-transfer level (RTL)-to-signoff flow. Incorporating knowledge of physically aware design early in the front-end design process is quickly becoming a must-have to enable faster convergence in the back end.

Join us at the Front-End Design Summit, where you can network with fellow logic designers and speak directly with Cadence® R&D experts from our Encounter® RTL Compiler, Encounter® Test, and Conformal® product teams. At this day-long technical event, you will:
  • Hear from Cadence customers the challenges they faced during logic synthesis, advanced low-power design and verification, engineering change order (ECO), and design-for-test (DFT) implementation, and the strategies they employed to address them
  • Discover how best to achieve power, performance, and area goals on industry-leading IP cores
  • Network, share your knowledge, and exchange best practices with your industry peers
  • Hear from Cadence R&D on product updates, solutions, and future directions
Win an Apple Mini iPad®! Drawing will be held at the end of the event.

Agenda
Time Title Speaker
9:00am Registration and Breakfast  
9:30am Welcome Andy Lin, VP of R&D, Front End Design, Cadence
9:55am Advantages of RTL Compiler Using Physically Aware Structuring Jaga Shanmugavadivelu, Cisco Systems
10:30am Addressing Physical Challenges Early in RTL Synthesis Ankush Sood, Cadence
11:00am Break  
11:15am ECO Experience on a High Performance Mobile ASIC Deepa Thali, Qualcomm
11:45am Optimizing PPA for Tensilica® BBE32 Core Jagesh Sanghavi, Cadence
12:15pm Lunch with R&D  
1:15pm Power-Efficient SmartScan Test Architecture for Processor Designs Alan Hales, Texas Instruments
1:45pm Addressing Test Challenges for GigaScale SoCs Michael Vachon, Cadence
2:15pm Advanced Verification for Imaging ASICs Simon Wong, Omnivision
2:45pm Break  
3:00pm Streamlining Your Verification Flow Kei-Yong Khoo, Cadence
3:30pm Bridging the Gap in an RTL2GSDII Flow Simon Kinahan, Cadence
4:00pm Final Q&A, iPad® Mini Drawing  
4:15pm Networking Event  

Questions About this Event?
Send email to events@cadence.com