Cadence is excited to be presenting at the ARM® Technology Symposium in Bangalore.
Measure and Optimize the System Performance of a Smartphone RTL Design
Presented by Nick Heaton, Distinguished Engineer, Cadence
ARM CoreLink™ System IP addresses the complexity of smartphone design by managing connections of the processing subsystem, memory subsystem, and an array of peripherals. These connected systems provide high performance while minimizing the device's thermal and power profile. To harness CoreLink's ability to support a variety of peripheral combinations, the designer must analyze the configured IP under a variety of use cases to ensure that performance requirements are met. This presentation will describe a way to measure and debug the performance of designs using the ARM CoreLink 400 series. Simulations for these implementations will be run for different use cases, giving a clear picture of how design decisions affect performance and what tradeoffs yield the best options and configurations. Included is the introduction of a new tool, Interconnect Workbench.
In the exhibit hall, Cadence will be showcasing the newly launched Tempus™ Timing Signoff Solution. To address the constantly growing signoff challenges, Tempus Signoff Solution offers massively parallelized timing analysis and physically aware multi-mode, multi-corner optimization for faster design closure and signoff. Learn more at our booth in the exhibition floor at the ARM Technology Symposium!
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