will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.
Home > About Cadence > Events > Event Details

Archived Webinar: Efficient, Exhaustive Register Map Validation

Original webinar date:
13 Nov 2013  
  View Webinar »  

Verification applications are rapidly emerging: packaged solutions leveraging powerful formal verification technology to solve difficult, but well-defined and commonly occurring verification problems. One such problem is the verification of correct register map access and absence of corruption, which is very difficult to check sufficiently in simulation. By using a new register validation app to generate properties automatically from your SPIRIT/IPXACT specification, you can exhaustively check a multitude of common register behaviors like value after reset, register access policies (RW, RO, WO, etc.), and inter-register dependencies including both frontdoor/backdoor access. Presented by product expert and user Jose Barandiaran, the goal of this webinar is to share:
  • Overview of verification apps available from Cadence
  • Common register validation problems
  • Detailed capabilities of the register validation app
  • Range of register access policies supported
The webinar will share how verification apps ease the adoption of powerful formal verification technology, previously the domain of a handful of formal verification experts. The presenter will present an overview of the range of applications that package this powerful technology and put it in the hands of verification engineers without deep formal expertise. He will then focus on the register validation problem, and how the register validation app achieves rapid exhaustive verification, giving clear real-world examples.

Who should attend?
  • Digital designers responsible for designing and/or verifying blocks with register maps
  • Verification engineers and verification leads interested in improving quality, productivity, and predictability of their verification process
  • Project managers and product managers interested in seeing how to slash timescales to achieve formally proven, exhaustive verification results

What you will learn
  • How to leverage verification apps to ease adoption of formal techniques
  • How to achieve exhaustive register verification against IP-XACT specification
  • How to verify all reset and access policies for your registers
  • How to debug register map issues found

Jose Barandiaran is currently a senior member of consulting staff at Cadence, responsible for Incisive® Formal product engineering. He has eight years experience with formal verification and five years of simulation verification experience at Cadence. Previously, he spent 10 years in verification engineering at Compaq/HP. He has a BSEE from Rochester Institute of Technology, and a MS in Engineering Management from UT Austin.

Questions About this Event?
Send email to

View Webinar »