More and more of today’s complex designs include analog functionality. The interactions and feedback loops between digital and analog functionality call for more functional verification of the whole mixed-signal design. However, because the simulation engines used for analog designs (SPICE, FastSPICE, etc.) run several orders of magnitude more slowly than a digital-only simulation, engineers are turning to fast real number models (RNM) to accurately simulate analog behavior for full chip verification. Watch this webinar to learn how you can achieve a significant speed-up in simulation performance (greater than 100Xx – 500Xx) by replacing the analog portions of your design with functionally equivalent RNM using real/wreal functionality in Verilog-AMS and/or SystemVerilog.
The IEEE P1800-2012 (SV) standard was published in February 2013 with several new features useful for real number modeling. Join this webinar to see how Cadence is leveraging this new functionality to provide behavioral modeling solutions to customers.
Who should attend?
- Verification engineers, verification leads, designers, and managers interested in improving the predictability, productivity, and quality of mixed-signal SoC verification runs
- Analog and mixed-signal SoC verification engineers looking to learn about event-based behavioral modeling techniques
- Digital and SoC verification engineers looking to achieve >100Xx – 500Xx performance improvements in their nightly regression runs
What you will learn
- What modeling features are available in the new IEEE P1800-2012 LRM
- How to use model constructs such as nettypes and wreal data types to dramatically improve top-level verification performance
- How to create RNM in SystemVerilog and Verilog-AMS
- How to enable mixed-signal verification very close to digital speeds using RNM for high-volume, digital-centric nightly regressions runs
Amar Dwaka is a member of the Product Expert Team at Cadence, specializing in real number modeling, analog/digital connectivity, and mixed-signal verification methodology. Amar has eleven years of design and verification experience and, prior to his five years at Cadence, was a mixed-signal design and verification engineer for IBM and the Naval Research Center. Amar is based in Austin, TX.
Questions About this Event?Send email to email@example.com