EPEPS is the premier international conference on advanced and emerging issues in electrical modeling, analysis, and design of electronic interconnections, packages, and systems. The event also focuses on new methodologies and design techniques for evaluating and ensuring signal, power, and thermal integrity in high-speed designs. EPEPS is jointly sponsored by the IEEE Components, Packaging and Manufacturing Technology Society and IEEE Microwave Theory and Techniques Society.
Visit Cadence at table #5, where you’ll learn about integration between Allegro® and Sigrity™ technology for both signal and power integrity. See the first public demonstrations of the IO-SSO Analysis Suite, a new product that addresses coupled signal, power, and ground across chip, package, and board to provide accurate system-level simultaneous switching noise (SSN) analysis.
Also, be sure to attend the following Cadence® speaker sessions:
Monday, Oct. 28
Accelerate High-Speed I/O Design Closure with Distributed Chip I/O Interconnect Model
Speakers: Yun Dai, Patrick Ho, Tiejun Yu, Jiayuan Fang
Accurate Characterization of Lossy Interconnects from TDR Waveforms
Speakers: Liu Ping, Zhang Jingping, Fang Jiayuan
Wednesday, Oct. 30
A Low-Frequency, Enhanced S-Parameter Handling Scheme for Time-Domain Simulation of High-Speed Interconnects
Speakers: Chong Luo, Jingping Zhang, Jiayuan Fang
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