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Signoff Summit: The Fastest Path to Design Signoff

Cadence Event  
21 Nov 2013  
Cadence Design Systems, San Jose, Building 10 Auditorium  

This is the first of a series of all-day Signoff Summits from Cadence that focus on the multiple facets of design signoff. This first summit will include keynote addresses plus sessions covering the multiple solution components that comprise a comprehensive signoff solution:
  • Power analysis and signoff
  • Parasitic extraction
  • Digital timing closure and signoff
  • Physical verification
  • Design for Manufacturing (DFM)
There will be extended focus on the new Cadence® timing and power signoff solutions: Tempus™ and Voltus™. The Tempus Timing Signoff solution, announced in May 2013, generated huge attention at DAC. Voltus is a new Power Signoff solution that raises the bar for power analysis and signoff.

In each session, you will learn more details about the solutions and hear experiences directly from customers. For timing and power signoff, there will also be on-stage demos to show you in detail how these solutions perform.

To close the summit, there will be a cocktail hour from 5pm to 6pm. Silicon Signoff and Verification R&D technical staff will be on-hand to answer your detailed questions, plus additional demos will be shown.

Who should attend?
  • Design engineers responsible for timing closure and signoff
  • Design engineers responsible for power analysis and signoff
  • Design/CAD engineers interested in learning about advancements in signoff solutions
  • Project managers interested in learning how the latest Cadence signoff solutions can be used to improve their design methodology

What you will learn
  • The latest information on each of the signoff component solutions
  • How each of the solutions can improve your design flows and methodology
  • Practical usage of the signoff solutions directly from customers
  • Live demos of all solutions

Time Title Speaker
8:30am Registration and Breakfast
9:00am Cadence Welcome, Overview, and Keynote
View presentation
Anirudh Devgan, Senior VP R&D
9:30am Defining Signoff Amidst the EDA-Foundry-Design Vortex
View presentation
9:50am Break
10:00am A Breakthrough in Power Signoff - The Voltus IC Power Integrity Solution
View presentation
Jerry Zhao, Cadence
10:30am High-Performance, Multi-CPU Scalable Power Signoff for Mega Designs
View presentation
Patrick Sproule, NVIDIA
11:30am Fast and Accurate Signoff Extraction for Advanced Node Designs
View intro presentation
View presentation
Kyle Peavy, Texas Instruments
12:00pm Incremental Signoff Metal Fill Flow Using Encounter, PVS, and QRC
View presentation
Takeyoshi Ikeda, Cadence
12:15pm Lunch
1:10pm Teething Signoff—You Have to Own It
View presentation
Jim Hogan, EDA Visionary and Investor
1:30pm Breaking the High-Performance Barrier in Timing Analysis and Signoff—The Tempus Timing Signoff Solution
Contact Ruben Molina for the presentation
Ruben Molina, Cadence
2:15pm Advanced Timing Solutions and Challenges—Statistical OCV, Path-Based Analysis, and Low-Voltage FinFET Modeling
View presentation
R&D, Cadence
3:00pm Break
3:15pm Transitioning to PVS
View presentation
Marie Luo, Conexant Systems
3:45pm Physical Verification Signoff for DDR IP Using PVS
View intro presentation
View presentation
Tobing Soebroto, Cadence IP Design
4:00pm Placement-Dependent Variability Assessment of Standard Cell Libraries
View presentation
Concetta Riccobene, LSI Logic
4:00pm Macro Modeling-Based Layout-Dependent Effect-Aware Custom Design Flow
View presentation
4:00pm Foundry-Certified DFM Services: A Alternative to Meet Mandatory DFM Requirements
View intro presentation
View presentation
Cadence DFM Services
5:00 pm Close and Reception Lip-Bu Tan, CEO, Cadence