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Technology on Tour: System-to-Silicon Verification

 
Type:
Cadence Event  
Date:
10 Oct 2013  
Location:
Ottawa, ON, Canada  

Verification has evolved into a complex process that often spans multiple teams and long development cycles, involving both hardware and software aspects. The process also includes learning and incorporating new methodologies, languages for hardware and software, design intellectual property (IP), verification IP (VIP), tools, and techniques.

In this full-day technical seminar, you’ll learn best practices and gain valuable insight from Cadence® functional verification experts. Our experts will discuss how to verify today’s complex systems on chips (SoCs) and systems and how to enable earlier embedded software development to shorten program schedules and get to market quicker. Discover the latest verification methodologies and techniques, such as:
  • Raising verification debug and advanced debug productivity
  • Managing functional and code coverage
  • Learning the foundations of formal verification and advanced applications
  • Implementing plan-driven verification with UVM and vManager
  • Integrating IP and VIP into your design and verification environment
  • 1801 CPF and UPF verification
  • Software-driven verification
  • SoC verification and hardware/software integration
  • Early firmware and software development and validation
Who should attend?
  • Digital and verification engineers
  • SoC integration engineers
  • Verification managers and executives
  • Hardware-aware embedded software developers
  • Software-aware hardware verification engineers
  • Anyone working on or considering advanced-node SoC verification projects
  • Anyone considering purchasing design IP and/or VIP
  • Anyone needing higher performance and productivity in their verification methodology

Agenda
8:30am Registration
9:00am Section 1: Designer verification including debug, formal verification, and code coverage.
10:20am Section 2: Advanced verification including advanced debug, IP and VIP, formal apps, SystemVerilog/UVM, and plan-driven verification
Noon Lunch
2:30pm Section 3: SoC verification methodology including SMART VIP, x-propagation analysis, low-power, hardware/software development, UVM-based acceleration, emulation, and FPGA-based prototyping
5:00pm Closing remarks and Q&A

Questions About this Event?
Send email to events@cadence.com