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Cadence at ARM TechCon 2013

 
Type:
Industry Conference  
Date:
29 Oct 2013 - 31 Oct 2013  
Location:
Santa Clara Convention Center, Santa Clara, CA  

Visit Cadence at ARM TechCon to learn more about our ARM® optimized solutions, from system to silicon.

Technical experts will be on hand to present papers and speak at the sponsored sessions on Wednesday, Oct. 30 and Thursday, Oct. 31.

Cadence Sponsored Sessions:
Time Description Company
Wed., Oct. 30, 10:30am Virtual Platform/Emulation Hybrid: High performance and RTL accuracy for system validation NVIDIA and ARM
Wed., Oct. 30, 11:30am Designing Analog-intensive Microcontroller for Internet of Things Applications Cadence
Wed., Oct. 30, 12:30pm Get Optimal PPA for Cortex™-A12/Cortex-A57 based SoCs with Encounter RTL-to-Signoff Solutions Cadence
Wed., Oct. 30, 1:30pm Modeling Physical Effects During Logic Synthesis to Improve Timing and Reduce Power Cadence
Wed., Oct. 30, 2:30pm Highly Scalable Multicore ARM Cortex-A15 Verification with Specman/e Texas Instruments
Wed., Oct. 30, 3:30pm Integrating DDR PHY IP into Your ARM SoC -- Challenges and Solutions Cadence
Thu., Oct. 31, 10:30am Earlier Software and Hardware Co-Development Using Virtualized Board on a Emulation Platform Broadcom and Cadence
Thu., Oct. 31, 11:30am Verifying the AMBA® 4 ACE protocol – at the interface and across the interconnect ARM and Cadence

Conference Papers:
Time Description Speakers
Tue., Oct. 29, 10:30am Maximizing Performance of ARM Cortex-A15 for Ultra-Power-Constrained Mobile Devices Paddy Mamtora, Cadence
Tue., Oct. 29, 1:30pm Creating the Industry’s First Cortex-A57 64-bit Processor on TSMC 16nm FinFET Process using Cadence design tools and ARM Physical IP Paddy Mamtora, Cadence
Tue., Oct. 29, 2:30pm Best Practices for Physical-Aware Synthesis and Implementation on Mali T6XX GPUs Sanjiv Taneja, Cadence
Wed., Oct. 30, 10:30am How to Measure and Optimize the System Performance of a Smartphone RTL Design William Orme, ARM and Nick Heaton, Cadence
Wed., Oct. 30, 11:30am Hardware, Software, and System Debug for ARM-Based Design Frank Schirrmeister, Cadence
Wed., Oct. 30, 11:30am Realizing High-Performance and Power-Efficient Implementations of ARM Cortex-A57 Processor at Advanced Process Nodes Raney Southerland, ARM and Paddy Mamtora, Cadence
Thu., Oct. 31 1:30pm Power, Performance, and Cost-Optimized ARM Cortex-A12 Implementation in 28nm SLP (Super-Low-Power) Technology Jeorge Winkler, GlobalFoundries and Dirk Siedler, Cadence

Paper Presentation
Cadence, ARM, and Samsung will be a presenting a joint paper, Samsung, ARM, and Cadence Collaborate on World's First Silicon-Proven 14-nm ARM Cortex-A7 FinFET CPU. Attend the session from 10:30am - 11:20am on Wednesday, Oct. 30, in Grand Ballroom H.

Panel
Cadence's Jim Ready, chief technology advisor, will take part in a panel discussion with his peers: "The Future of Collaborative Embedded SW Development, from the Viewpoint of One Technology Chain Gang." Don't miss this exciting session, 3:30pm – 4:15pm Oct. 30, at the Expo Theater.

Cadence Demos
In the exhibit hall, at booth #600, you'll see demos in the following areas:
  • Implementing High-Performance and Power-Efficient ARM Cortex-A Processors at Advanced Nodes
    • Physically aware synthesis with Cadence Encounter® RTL Compiler
    • Cadence Encounter Digital Implementation System featuring GigaOpt and Clock Concurrent Optimization (CCOpt) technologies
  • Faster Design with Standards-Based Intellectual Property (IP)
    • Memories, interfaces, analog, and peripheral IP
    • Verification IP for memories and complex protocols
  • System-to-Silicon Verification
    • Cadence System Development Suite featuring ARM Fast Models
    • Functional verification featuring low power, management regression, and debug
  • Mixed-Signal Flow for Embedded Cortex-M Designs
    • Functional and low-power verification covering analog, digital and software
    • Smooth path to silicon using Integrated Mixed-Signal Physical Implementation Flow

Questions About this Event?
Send email to events@cadence.com