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Cadence Event at ITC 2013

Cadence Event  
09 Sep 2013 - 12 Sep 2013  
House of Blues – Anaheim, CA, USA  

RSVP for Cadence Event

Join Cadence for an evening reception at the House of Blues, Anaheim from 7:00pm to 9:00pm on Wednesday, September 11. This special event for Cadence® customers is a great opportunity to network with colleagues, chat with Encounter Test architects, and have a little fun.
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Meet with Cadence R&D and Discuss Your Technical Needs
Cadence is once again a Silver Sponsor for ITC 2013. Our Encounter® Test R&D team will be participating in tutorials, technical sessions, and panels. In addition, you are invited to set up a meeting with us to discuss your interests and needs.

Please contact Lisa Jensen ( to arrange a private meeting time that fits your schedule between 9:00am and 5:00pm on Tuesday, September 10, and on Wednesday, September 11.

Cadence Activities at ITC 2013
Monday, September 9
1:00pm – 4:30pm
  • Tutorial 12 - Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry Practices
    S. Ravi, V. Chickermane, K. Chakravadhanula

Tuesday, September 10
2:00pm – 3:30pm
  • Technical Paper – Session 3 - 2.5D/3D-IC DFT, E.J. Marinissen, IMEC (Chair)
  • 3.1 Test and Debug Strategy for TSMC CoWoS Stacking Process-based Heterogeneous 3D-IC: A Silicon Case Study
    S.K. Goel, S. Adham, M-J. Wang, J-J. Chen, T-C. Huang, A. Mehta, F. Lee, TSMC; V. Chickermane, B. Keller, T. Valind, S. Mukherjee, N. Sood, Cadence; J. Cho, H-H. Lee, J. Choi, S.Kim, SK Hynix

Tuesday, September 10
4:00pm – 5:30pm
  • Technical Paper – Session 4 - Scan Compression for Large Designs, S. Ravi, Texas Instruments India (Chair)
  • 4.2 SmartScan - Hierarchical Test Compression for Pin-limited Low-Power Designs
    K. Chakravadhanula, V. Chickermane, D. Pearl, A. Garg, R. Khurana, S. Mukherjee, P. Nagaraj, Cadence

Thursday, September 12
2:00pm – 3:30pm
  • Panel 5 - The Battle of the Standards, S. Adham, TSMC (Moderator) — R. Kapur, Synopsys (Organizer)
    Three IEEE standards are developed to address test problems at different integration levels (core, chip and system). These standards overlap in some aspects and might complement each other in other areas. In this panel, IEEE test standards experts will debate the value of each standard and present the infrastructure required to use the standard in a design. Panelists will also provide their view on if and how all these standards may co-exist in the future.
    • C.J. Clark, Intelletech
    • A.Crouch, ASSET InterTech
    • B. Keller, Cadence
    • T. McLaurin, ARM
    • K. Parker, Agilent
    • J. Rearick, AMD
3D-TEST Workshop
Cadence is also participating in the 3D-TEST Workshop . Register at

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