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Archived Webinar: Accelerate PCB Routing by Optimizing FPGA Pin Assignments

Orignal webinar date:
12 Sep 2013  
  View Webinar »  

Attend this hour-long webinar to learn how you can accelerate routing and reduce PCB layer counts by optimizing FPGA pin assignments during placement and route planning. This session will highlight the capabilities of Cadence® Allegro® FPGA System Planner and Cadence Allegro PCB Editor.

Who should attend?
  • PCB designers
  • Hardware designers
  • FPGA designers

What you will learn
  • How to use Interconnect Flow Planner inside Allegro PCB Editor to identify FPGA pins that need to be swapped
  • How you can use Allegro FPGA System Planner as an engine inside Allegro PCB Editor to propose FPGA pin assignments based on FPGA vendor rules to shorten routing time and possibly reduce PCB layer counts

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View Webinar »