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Live Online Q&A with Cadence Memory IP Tech Experts

 
Type:
Cadence Event  
Date:
17 Sep 2013  
Location:
Online  

Join us for a unique opportunity to learn more about memory intellectual property (IP) directly from Cadence® technical experts. Our panel will take part in an hour-long, live online Q&A, where you can post your toughest questions for them to tackle.

When: 11:00am to 12:00pm PST, Tuesday, September 17
Where: Online, from the comfort of your desktop or mobile device
Topics: Challenges and solutions around the latest memory standards, such as DDR4, Wide I/O 2, LPDDR4, Hybrid Memory Cube, and High Bandwidth Memory

Aside from asking questions, you’ll also be able to share comments or your own insights during this session. And, you’re welcome to simply watch and learn!

Today’s Panelists
Tom Hackett, our host today, is a product marketing director at Cadence, where he supports the Cadence® Verification IP Catalog and storage protocols. He has a BSEE from West Virginia University and began his career as a design engineer at Texas Instruments.
Gopal Raghavan, a Cadence fellow, is a well-known memory expert and is responsible for areas including IP roadmap development, SoC integration, and performance evaluation. He has electrical engineering degrees from the Indian Institute of Technology (bachelor’s) and from Stanford University (M.S. and Ph.D.).
Wendy Elsasser, a DDR IP architect at Cadence, has more than 15 years of experience in design and architecture of SoC subsystems. She has a bachelor’s in electrical engineering from the Georgia Institute of Technology and a master’s in electrical engineering from the University of Illinois.
Kishore Kasamsetty is a product marketing director at Cadence, where he focuses on memory design IP. He has a MBA from the University of California at Los Angeles and electrical engineering degrees from the University of Minnesota and Birla Institute of Technology & Science in India.
Scott Jacobson is a sr. product marketing manager at Cadence, where his focus is the memory model portfolio and Ethernet protocols. He has a BSEE from Washington State University, and began his career as a design engineer at Boeing Aerospace.
Robert Adams is the director of the Cadence R&D Memory Model team and has worked for Cadence and Denali, which Cadence acquired in 2010, for over 15 years. Robert graduated from Purdue University with a MSEE degree.

Questions About this Event?
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