will be under system maintenance from Tuesday June 28, 6pm PT to Sunday July 3, 11pm PT. Login and registration will be disabled.
Home > About Cadence > Events > Event Details

Archived Webinar: 6 Must-Know Tips to Optimize LPDDR and Wide I/O Performance

Original webinar date:
25 Jun 2013  
  View Webinar »  

Should your next design incorporate LPDDR3 or Wide I/O? Should you leapfrog to LPDDR4 or Wide I/O 2? How would this impact your controller and PHY implementation? The most successful mobile products combine higher performance with lower power dissipation. Memory subsystem design is key to delivering both, but the implementation choices are not always clear. Watch this 30-minute, pre-recorded webinar today to get some answers and learn the six must-know tips to optimize LPDDR and Wide I/O performance.

Who should attend?
  • Designers interested in designing next-generation memory controllers and PHYs
  • Designers wanting to evaluate trade-offs between power, bandwidth, and cost

What you will learn
  • Comparisons of memory topologies between LPDDR3, LPDDR4, and Wide I/O2
  • What’s better: wide vs. fast?
  • Other things you should consider

Questions About this Event?
Send email to

View Webinar »