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Signal Integrity Technology on Tour

Cadence Event  
13 Sep 2013 (8:45am - 5:00pm)  
Singapore Marriott Hotel, Grand Ballroom (Level 3), 320 Orchard Road, Singapore  

Increasing demands for complex, high-end ICs and chip-package-PCB integration are driving greater demands for low power and high-speed data transmission rates. For design engineers, this also means bigger challenges in the areas of signal integrity and power integrity. Attend the Cadence Signal Integrity Technology on Tour to learn best practices and useful insights to meet these challenges, directly from our Allegro® Sigrity™ experts.

Seats are limited; register before September 6 to reserve your spot.

Who should attend?
  • Design engineers working on projects at the chip, package, and/or system levels
  • Designers who need solutions that address high-speed power integrity, signal integrity, and thermal issues

What you will learn
  • Insight into high-speed design challenges associated with power integrity, signal integrity, and thermal issues
  • How to address issues associated with 2.5D/3D-IC packaging and PCB system-level simulation

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