Final signoff timing closure is fast becoming the largest bottleneck in getting designs to tapeout. Inherent differences in timing results between place-and-route tools and signoff-timing tools result in numerous ECO loops to close on design timing. In addition, optimization fixes in signoff are performed without regard to realistic placement of inserted cells. At the lower process nodes, an increased number of operating modes and process-voltage-temperature (PVT) corners has increased the number of timing views that need to be optimized across. The increased amount of analysis, coupled with the miscorrelation to implementation tools, has resulted in untenable solutions with today’s tools.
In this webinar, you’ll learn how the new Cadence® Tempus™ Timing Signoff Solution addresses this impending challenge of performing analysis and optimization across large numbers of timing views. We will focus on the keys to this solution, which include the analysis flow and scalability with increasing number of timing scenarios, the ability to understand and intelligently utilize physical information from the place-and-route environment during optimization, and the kinds of optimization that are available to the user.
Join us to see how Cadence can address your timing signoff closure problems today.
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