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System-to-Silicon Verification Summit

 
Type:
Cadence Event  
Date:
26 Sep 2013  
Location:
Cadence Design Systems, Building 10 Auditorium, San Jose, CA  

Cadence Summits assemble industry leaders and technology experts from customers, partners, and Cadence to discuss and debate the toughest challenges facing the EDA industry. On September 26 Cadence held the first annual System-to-Silicon Verification Summit at Cadence’s San Jose offices. If you missed the presentations and debates, the archived proceedings are available below.

Proceedings
Topic Speaker Proceedings
Cadence Welcome/Overview Charlie Huang, Sr. Vice President, R&D, Cadence
The Business of Verifying Modern Systems-on-Chip and Software: How to Make Sure That Energy and Performance Envelopes are Met and What's the Cost of Missing Them? Jim Hogan, EDA Visionary and Investor
Verification 2.0: Transformation from Tool to Flow Brian Bailey, Engineering Consultant and EETimes DesignLine Contributing Editor
Enabling Early Hardware/Software Co-Verification with Palladium XP II Kent Goodin, Executive Vice President, Engineering, Zenverge
Accelerating Embedded OS and Software-Driven Verification Vik Singh, Senior System Software Manager, NVIDIA
Panel: Challenges in System-to-Silicon Verification Moderated by Gary Smith, Chief Analyst of Gary Smith EDA Firm
X-Propagation: Verifying the Initialization Sequence Lukito Muliadi, Senior Design Manager, Ambarella
Shorter System Development Cycles Demand Software and Hardware Co-Verification Mehran Ramezani, Senior Manager, Firmware, Mobile and Wireless Group/SoC, Broadcom
Verification Runtime Performance Tuning Ross Smith, Ph.D., IC Design Scientist, Broadcom DVT
FPGA-Based Rapid Prototyping – Help or Distraction for Embedded System Development? Juergen Jaeger, Product Marketing Manager, Cadence
SoC Interconnect Verification and Performance Analysis Herbert Rivera-Sanchez, Solutions Architect, Cadence