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Archived Webinar: Analog Behavioral Modeling and Model Generation

Original webinar date:
25 Jul 2013  
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Analog Behavioral Modeling and Model Generation

Mixed-signal design engineers face increasing difficulties in design and verification of complex mixed-signal SoCs. Utilizing analog behavioral models can yield simulation performance improvements that can make full chip verification a reality. However, for true performance improvement, you need to understand and set the correct modeling goals and also choose the right language. There are, afterall, varying levels of abstraction models to bridge the large disconnect between performance modeling for analog verification and functional verification at the SoC level. This webinar covers behavioral modeling challenges and introduces real number models for functional behavioral modeling. The session introduces Cadence’s recommendations to generate and validate behavioral models within the Virtuoso® design environment Schematic Model Generator (SMG) and AMS Design & Model Validation (amsDmv).

Date and Time
1000am CET (9am GMT) on Thursday, July 25, 2013

Who Should Attend
  • Analog designers, including those with little modeling experience
  • Mixed-signal verification engineers
  • Top-level verification engineers
  • Mixed-signal design engineers
  • Modeling experts

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