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Technology on Tour: Mixed Signal/Low Power

 
Type:
Seminar  
Date:
23 Jul 2013  
Location:
Hotel Equatorial Penang, Penang, Malaysia  

Mixed-signal and low-power applications are two of the fastest growing market segments in the electronics and semiconductor industries. Applications for mobile communications, networking, power management, automotive, medical, imaging, internet of things, safety, and security require a very high integration of analog and digital functionality at system, system-on-chip (SoC), and IP levels. Along with design complexity, low-power requirements are becoming paramount in these designs due to the mobile revolution. Designers must upgrade their existing methodologies, or adopt new ones, to keep up with mixed-signal design complexity and satisfy the low-power requirements of various applications.

In this full-day technical seminar, you’ll learn best practices and gain valuable insight from Cadence® mixed-signal and low-power R&D experts. Hear how to realize today’s highly integrated mixed-signal designs more productively and profitably while meeting the low-power requirements. Discover the latest mixed-signal low-power methodologies and techniques, such as:
  • Traditional analog and mixed-signal verification with a newly developed simulation engine
  • Digital-enabled mixed-signal verification with analog behavior modeling
  • Verifying the low-power intent of mixed-signal designs with dynamic and static methods
  • Critical IP for mixed-signal designs
  • Analog and mixed-signal design at advanced nodes
  • RTL to GDS2 low-power flow for power estimation and implementation
You’ll also hear case studies of how design teams are successfully using Cadence mixed-signal and low-power solutions to achieve their tapeout goals, optimize performance and power, reduce development costs, and improve turnaround time. Don’t miss this opportunity to resolve your design challenges and network with other expert users and Cadence technologists.

Who should attend?
  • Circuit designers
  • AMS and SoC verification engineers
  • Low-power architects
  • Digital P&R engineers
  • CAD engineers and managers
  • Design managers
  • Anyone involved with realizing low-power mixed-signal designs in silicon

What you will learn
  • Insight into the latest mixed-signal verification, implementation, and signoff methodologies to improve productivity and first-silicon success
  • Techniques and tips to differentiate your designs using advanced low-power techniques
  • Recommendations, based on silicon-proven successes, for effectively deploying new methodologies in your design environment today
  • Key insight in to Cadence IP portfolios for mixed-signal designs

Agenda
Start Time Session
8:45 Registration and Breakfast
9:30 Welcome and Opening Remarks
9:35 Cadence Mixed-Signal Verification Solution Overview
9:50 Analog-Centric Mixed-Signal Verification
10:20 Analog Behavioral Modeling Real Number Modeling, Model Generation (SMG), Model Validation (amsDMV)
DEMO: SMG and amsDMV
11:00 Break
11:15 Low-Power Verification for Mixed-Signal Designs CPF-Aware AMS-Designer and Virtuoso® PIEA for Macro Model Generation
DEMO: AMS-D CPF and PIEA
11:55 Introduction to Cadence IP Portfolio for Analog/Mixed-Signal Designs
12:15 Lunch
13:30 Analog/AMS Design at Advanced Nodes
14:30 RTL-GDS2 Power Estimation
15:00 Break
15:15 RTL-GDS2 Low-Power Flow
16:15 Low-Power Standards Update
16:45 Wrap-Up and Lucky Draw

Questions About this Event?
Send email to event_ap@cadence.com