Custom IC Technology Day: Advanced Analog and Mixed-Signal Design
|09 Jul 2013 - 10 Jul 2013
Join us for a technology day of lectures and hands-on workshops. You will learn best practices and gain valuable insight from Cadence experts, about the advanced flows and new technology in the latest releases of Virtuoso® platform tools. We will focus on how to increase verification and predictability during design stages, in order to reduce the number of design-layout iterations and total design effort. Discover the latest custom and analog methodologies and techniques, including:
Who should attend?
- Analyze DFM effects (WPE, LOD/STI etc.) as soon as devices are placed – without the need to have an LVS clean layout.
- Understand how the Electrical Aware Design flow (EAD) helps you analyze Rs & Cs and Electromigration hazards simultaneously as the layout shapes are being drawn.
- Model and simulate parasitics of signals passing from chip, through its package onto PCBs in an integrated flow.
- Special considerations of 20nm/16nm design with FinFETs, local interconnect and double patterned masks.
- Correct by construction layout – with on-line DRC, LVS and constraint checking in both interactive & assisted chip layout.
- Manage variability across multiple corners with ADE-XL Sensitivity Analysis, Monte-Carlo Analysis and High Yield Estimate/Improvement.
- Efficient use of Spectre/APS accurate spice simulator, for maximum speed and capacity including optimized settings, EM/IR analysis, Design Checks, and Analog assertions.
Dates & Location:
- Analog, RF and Mixed-Signal designers
- Layout designers
- Verification engineers performing Mixed-Signal integration
9 July 2013 - Cadence Herzliya Training Center
10 July 2013 - Cadence Herzliya Training Center Agenda
|08:45 – 09:00
||Registration & Coffee|
|09:00 – 09:30
||Welcome and Introduction|
|09:30 – 10:30
||Electrically Aware Design and Managing Layout Dependent Effects|
|10:30 – 11:10
||Links to Packaging – SiP Flows with Sigrity Field Solver |
|11:10 – 11:20
||Track I – Layout
||Track II - Design|
|11:20 – 12:20
||Correct by Construction Layout in IC616
||Advanced Analog Verification with ADE-XL |
|12:20 – 13:00
||Introduction to FinFET & Double Patterning for ≤ 20nm
||Maximum Capacity, Speed & Verification with Spectre Simulator|
|13:00 – 14:00
|14:00 – 17:00
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