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PCI-SIG Developers Conference 2013

Industry Conference  
25 Jun 2013 - 26 Jun 2013  
Santa Clara, CA  

Cadence is a platinum sponsor of this year’s PCI-SIG Developers Conference at the Santa Clara Convention Center. We will be showcasing the Cadence® low-power silicon-proven IP for PCI Express (PCIe) Gen3 as well as our complete families of verification and design IP. Cadence offers a unique differentiated IP capability with design, verification, and system integration.

Stop by booth #9 to see our demos:
  • Mobile PCIe (M-PCIe) controller working with a mobile PHY
  • Verifying protocol compliance with TripleCheck
  • PCIe Gen3 high-throughput controller
  • Chip-package-board design and analysis
Two Cadence experts will be presenting:
  • “Testing and Verification of NVMe PCIe Devices” by Moshik Ruben, 10:20am – 11:30am, Tuesday, June 25
  • “MPCIe Implementation Case Study” by Martin James, 3:30pm – 4:30pm Tuesday, June 25
For more details or to sign up for PCI-SIG DevCon, visit their web site

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