Multi-language (ML) verification is evolving. Early solutions enabled data exchange between SystemVerilog, e, C/C++, and SystemC verification environments. Eventually, users found that additional features are required to share, coordinate, and align independent environments. The UVM-ML open architecture delivers these features in simulator-independent, open-source format. The UVM ML Open Architecture implements a unified hierarchy, phasing, and control for multi-language verification environments, and includes full support for TLM1 and TLM2.
This webinar explains the challenges of existing “quick stich” solutions and the requirements driving the new open source solution. During the session, you’ll learn about technical details including a demonstration of the work completed to date by Advanced Micro Devices (AMD) and Cadence. This collaborative effort has achieved an important milestone that the architects from both companies are ready to introduce and for which they are ready for feedback.
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