Your design team has entered sub-65nm territory, and you have a tight leakage power budget. Knowing this, you’ve coded your power intent file to use power shut-off (PSO), as this is the most effective way to prevent leakage. In this webinar, using the example in the low-power Rapid Adoption Kit (RAK), you’ll learn how the native Cadence® Incisive® Simulator enables power-management techniques without a large methodology change or fundamentally changing your tool flow. The register-transfer level (RTL) contains no explicit logic to model low-power behaviors related to simulation during the power-down process for situations like state loss, state retention, and port isolation. As a result, the simulator must instead create implicit logic to model these behaviors. The simulator infers this implicit logic from the commands in the power intent file. This webinar walks you through the power format file using the example design provided in the RAK, and outlines the implicit logic inferred from the power intent file. You’ll also see a demo of the latest Cadence low-power verification debug applied to the example, and learn how to download the RAK for your own use.
Who should attend?
- Verification engineers and leads who are building verification environments for low-power designs
- Project managers planning low-power verification projects
- Design and verification managers looking to improve verification productivity and overall product quality
What you will learn
- The power format commands that lead to implicit modeling in simulation
- Verification implications of low-power modeling in simulation
- The latest low-power verification and debug capabilities from Cadence
- Details regarding the RAK example and how to access it
Questions About this Event?Send email to email@example.com