Home > About Cadence > Events > Event Details

Archived Webinar: A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence Tools

 
Type:
Webinar  
Orignal webinar date:
23 May 2013  
Location:
Online  
  View Webinar »  

Rahul Deokar and John Stabenow of Cadence and Jason Chen from TSMC will present, “20nm Design Methodology: A Completely Validated Solution for Designing to the TSMC 20nm Process Using Cadence Encounter®, Virtuoso, and Signoff tools.” You’ll learn about:
  • The TSMC-Cadence solutions in the TSMC 20nm Reference Flow, tools certification, and Cadence tools and methodology to enable 20nm design with double patterning technology (DPT)-aware capabilities, to reduce design complexities and deliver required accuracy
  • How in-design DPT and design rule checking (DRC) can improve your productivity
  • How both colored and colorless methodologies are supported, and data is efficiently managed in front-to-back design flows
  • How local interconnect layers, SAMEMASK rules, and automated odd-cycle loop prevention are supported
  • How mask-shift modeling with multi-value SPEF is supported for extraction, power, and timing signoff

Questions About this Event?
Send email to webinar_info@cadence.com

View Webinar »