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Mixed-Signal Technology on Tour: Best practices and valuable insight from Cadence mixed-signal R&D experts

 
Type:
Cadence Event  
Date:
25 Apr 2013 - 09 May 2013  
Location:
Phoenix, AZ – April 25, 2013
Minneapolis, MN – April 30, 2013
Colorado Springs, CO – May 2, 2013
Dallas, TX – May 7, 2013
Austin, TX – May 9, 2013
 

Mixed-signal applications are one of the fastest growing market segments in the electronics and semiconductor industries. Applications for mobile communications, networking, power management, automotive, medical, imaging, internet of things, safety, and security require very high integration of analog and digital functionality at system, SoC, and IP levels. Designers need to upgrade their existing methodologies, or adopt new ones, to keep up with mixed-signal design complexity.

In this full-day technical seminar, you’ll learn best practices and gain valuable insight from Cadence® mixed-signal R&D experts on how to realize today’s highly integrated mixed-signal designs more productively and profitably. Discover the latest mixed-signal methodologies and techniques, such as:
  • Modeling analog behavior with highly effective real number models
  • Applying assertion-based, metric-driven verification
  • Verifying low-power intent with dynamic and static methods
  • Floorplanning and integrating designs in a seamless, OA-interoperable flow
  • Analyzing timing and power for complex SoCs to prevent silicon re-spins
You’ll also hear case studies of how design teams are successfully using Cadence mixed-signal solutions to achieve their tapeout goals, optimize performance and power, reduce development costs, and improve turnaround time. Don’t miss this opportunity to resolve your design challenges and network with other expert users and Cadence technologists.

Who should attend?
  • Circuit designers
  • AMS and SoC verification engineers
  • Analog/custom layout engineers
  • Digital P&R engineers
  • CAD engineers and managers
  • Design managers
  • Anyone involved with realizing mixed-signal designs in silicon

What you will learn
  • Techniques and tips to enhance your mixed-signal flow
  • Insight into the latest mixed-signal verification and implementation methodologies
  • Recommendations, based on silicon-proven successes, for effectively deploying new methodologies in your design environment today

Agenda
9:00am Registration and Breakfast
9:30am Welcome and Opening Remarks
9:45am - Mixed-Signal (MS) Solution Overview
- MS Trends and Challenges
- MS Verification Overview
- MS Implementation Overview
- Verifying Low Power in MS design
- Static Timing Characterization for MS Ecosystem
10:15am - Mixed-Signal Simulation
- Performance and Scalability
- Use Models and Language Support
10:45am - Analog Behavioral Modeling
- Why Do I Need Modeling?
- Real Number Modeling
- Model Generation and Validation with Demo
11:30am - Simulating Embedded ARM Cortex-M0 MS Designs
- Trends in Analog Intensive MCU
- ARM Cortex-M Introduction
- HW/SW Verification Flow with Demo
12:00pm Lunch Cadence
1:00pm - Advanced MS Verification
- Assertions, UVM-MS and Metric-driven Methodology
1:30pm - Quick Turn-around Time with Cadence Analog/Mixed Signal (AMS) IP
- AMS Interface IP
- ADC’s, 10G-KR PHYs
- Cadence AMS IP Portfolio
2:00pm - Analog on Top (AoT) MS Implementation Flow
- AoT Flow Overview
- Virtuoso Floorplanning and Analog Layout
- Digital Block Synthesis and Implementation in RC/EDI
- Chip Integration and Signoff
3:00pm Customer Presentation
3:45pm Break
4:00pm - Digital on Top (DoT) MS Implementation Flow
- DoT Flow Overview
- Constraint (Routing) Exchange and Validation with Demo
4:30pm Wrap-up

Questions About this Event?
Send email to events@cadence.com