ISQED emphasizes a holistic approach toward design quality to highlight and accelerate cooperation among the IC Design, EDA, semiconductor process technology, and manufacturing communities. It provides a forum to exchange ideas and promote research, development, and application of design techniques and methods, design processes, and EDA design methodologies, and tools that address issues that impact the quality of designs into physical integrated circuits.
As part of this forum, Sanjiv Taneja , Vice President, Product Engineering at Cadence will present “Physical-Aware, High-Capacity RTL Synthesis for Advanced Nanometer Designs” on Wednesday March 6 at 8:15AM in the Silicon Valley ballroom. The small world of sub-20nm design is already upon us and has brought a new set of challenges for RTL designers as the race for best PPA (performance, power, and area) continues unabated. This talk will explore these challenges and provide an overview of state-of-the-art technology to address them in a predictive and convergent design flow.
Sanjiv Taneja is VP of Product Engineering for the Front End Design Group at Cadence Design Systems. Prior to assuming this role in 2010, he led Cadence's Encounter Test R&D group for over five years. He joined Cadence from Bell Laboratories where he led the development of transistor-sizing based technology for low power design. Sanjiv holds a BS degree in EE from IIT New Delhi, MS in Computer Science from Ohio State University and MBA from NYU.
This important three-day event is packed full of tutorials, additional keynote speeches, panel discussions, and in-depth technical sessions. The program will also feature the following:
- Full-day information-packed tutorials
- Keynotes by major industry and academia leaders and experts
- Latest trends in electronic design and automation, and semiconductor technologies
- Interact and network with the Experts and industry movers and shakers