The PCI-SIG is returning to Israel for the PCI-SIG Developers Conference Israel 2013! This year's event is focusing on the most up-to-date PCI technology. Cadence will showcase its integration-ready, proven PCI® Express solutions.
Cadence will demonstrate design and verification IP that supports PCI Express 3.0 specification. With dozens of designs taped-out using its PCI Express 3.0 IP and more than 200 designs verified with its PCI Express 3.0 VIP, Cadence highlights how customers can rapidly design and verify ASIC or SoC devices for emerging PCI Express 3.0 applications like storage, supercomputing, enterprise and networking. The company will highlight its PCI Express 3.0 controller IP, as well as verification IP and design-in kits for package-to-board implementation.
Design IP DemonstrationCadence is demonstrating a high-performance, dual-mode, 128-bit data-path, x8 PCI Express 3.0 controller configuration implemented in silicon on an advanced-node PMC-Sierra ASIC. The Cadence PCI Express 3.0 controller is integrated in an ASIC on a reference card which connects to a PCI Express Gen3 backplane exerciser and a PCI Express Gen3 logic analyzer to demonstrate PCI Express 3.0 traffic running at 8 GT/s per lane. Complying with v1.0 of the PCI Express 3.0 standard and v0.9 of the Intel PIPE 3.0 specification, the Cadence PCI Express 3.0 design IP has been successfully implemented in silicon with advanced capabilities like Single-Root I/O Virtualization (SR-IOV) and the latest engineering change notices (ECNs) such as ID-based Ordering, Re-Sizeable BARs, Atomic Operations, Transaction Processing Hints, Optimized Buffer Flush/Fill, Latency Tolerance Reporting and Dynamic Power Allocation. The Cadence PCI Express 3.0 IP has already been implemented in the recently announced PMC-Sierra 6Gb/s SAS Tachyon protocol controller.
Verification IP DemonstrationCadence will also demonstrate its PCI Express 3.0 VIP solution. The demonstration will show the unique TripleCheck for the PCI Express protocol which provides interactive, graphical analysis of coverage results correlated directly to the protocol specification, with thousands of test cases to simulate PCI Express traffic and check for compliance with the PCI Express specifications.
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