Today's electrical engineers face unprecedented challenges due to increasing design density (miniaturization), complexity, and faster edge rates. Some of the most complex interfaces designed in today’s high-end PCBs are the DDR3 memory interfaces. For a successful implementation, DDR3 requires in-depth timing and signal analysis at the pre-layout phase for constraint development, as well as a detailed simulation once the layout design is completed for signoff.
Cadence has created a complete DDR3 design-in kit that enables engineers to perform the necessary design and simulation tasks through a GUI-driven step-by-step approach. This workshop takes users through the steps required to use the DDR3 design-in kit. Upon completion, users will be able to use the kit on their own DDR3 memory interface designs.
For more information on IPC ESTC 2013, visit estc.ipc.org
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