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DesignCon 2013

Industry Conference  
28 Jan 2013 - 31 Jan 2013  
Santa Clara, CA  

DesignCon is the largest meeting of board designers and the only event to specifically address chip/system/package design challenges.

In our booth #607, Cadence will be exhibiting our industry leading Sigrity and Allegro technologies. We will show how Allegro and Sigrity together provide a power-aware signal integrity solution for DDR3/DDR4 interface design and provides the first comprehensive PCB design and analysis memory interface solution. In addition, we will show multi-gigabit interfaces, such as PCI-Express 3.0, being simulated by AMI models with back-channel support. Our compliance kits allow technologists to quickly determine if a channel is designed to meet the interface specifications.

Stop by and talk to our Sigrity and Allegro experts and how the tools when used separately or together, can help you with efficient product creation. Our experts will take you step-by-step from silicon to package to board, showing you the latest enhancements to our PCB and IC packaging design and analysis products.

The Cadence booth will feature the following demonstrations:
  • DDR3/DDR4 power-aware SI analysis including timing closure
  • Power Integrity – AC / DC analysis and decoupling optimization
  • Serial link SI analysis
  • Chip-package-board optimization (co-design and co-analysis)
And don’t miss the following conference papers:
  • Wed, Jan 30, 8:30 - 9:10: Using Power Aware IBIS V5.0 Behavioral IO Models to Simulate Simultaneous Switching Noise
    • Speaker: Romi Mayder, SI/PI Engineer, Xilinx
    • Speaker: Brad Brim, Sr. Staff Product Engineer, Cadence
    • Speaker: Yingxin Sun, Sr. Architect, Cadence
  • Wed, Jan 30, 11:05 - 11:45: Multi-Level Hierarchical Flow for Giga-Scale ASIC Designs
    • Speaker: Shashank Prasad, Senior Member of Consulting Staff, Cadence Design Systems
    • Speaker: Kamal Preet Singh, Member of Consulting Staff, Cadence Design Systems
  • Thurs, Jan 31, 10:40 - 11:20: Efficient Symbolic Circuit Analysis-Based Transfer Functions and Input Impedance Computations for Core-Power Delivery Network with VRM
    • Speaker: Om P. Mandhana, Senior Staff Product Engineer, Cadence Design Systems, Inc.

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