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ARM Technology Conference 2012
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Type: |
Conference & Exhibition |
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Date: |
30 Oct 2012 - 01 Nov 2012 |
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Location: |
Santa Clara, CA |
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At ARM TechCon 2012, Cadence technologies and solutions for ARM-based designs will be prominently featured throughout the three-day event. Check out our exhibit in Booth 36 (day 1) and Booth 417 (days 2 and 3). Don’t miss our paper presentations and sponsored sessions throughout the event. Cadence and ARM have collaborated successfully for decades on the design and verification of high-performance ARM core-based designs. We offer an optimized solution that includes a full set of interoperable tools with ARM processors and physical IP services, from system to silicon. Find out how the Cadence-ARM partnership is enabling customers to build revolutionary electronics products with verified, reusable hardware and software IP blocks—faster and with greater confidence that their systems will be manufacturable on first pass.
What you will see
Day 1: Chip Design Conference – October 30
- Cadence Booth #36
- RTL-to-GDSII flow for ARM Cortex-A processors
SoC designers in the consumer, mobile, computing, and wireless markets are moving ahead with 32/28nm and 20nm processes and pushing the boundaries of complexity, process variation, power, and performance. Cadence will demonstrate how to optimize power, performance, and area for ARM core-based designs at advanced nodes using the Encounter RTL-to-GDSII flow.
- Embedded Cortex-M0 system verification
Cadence will demonstrate mixed-signal simulation of a system with embedded ARM Cortex M0.
- Sponsored Sessions – Room #204
- 10:30 – 11:20 Automating the verification of SoC interconnect fabrics
Huzaifa Dalal, Senior Product Marketing Manager – VIP, Cadence and Mirit Fromovich, Staff Solutions Engineer, Cadence
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11:30 – 12:20 Power efficient big.LITTLE™ processing: lessons learned from a 28nm multi-core Cortex-A7 low-power implementation
Paddy Mamtora, Group Director, Cadence
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1:00 – 1:50 Designing with 14nm FinFET Technology
Lars Liebman, STSM, Distinguished Engineer, Design-Technology Co-Optimization, IBM
Vassilios Gerousis, Distinguished Engineer, Cadence
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2:10 - 3:00 Implementing Advanced Next Generation Mali T6XX GPUs with Cadence Encounter Digital Flows
Sanjiv Taneja, Vice President, Research and Development, Cadence
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3:10 – 4:00 Designing mixed-signal with ARM Cortex™-M0
Sathishkumar Balasubramanian, Senior Technical Marketing Manager, Cadence
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4:10 – 5:00 Optimizing Power Efficiency in GHz+ Quad-core ARM Cortex-A15 Processor Hardening
Paddy Mamtora, Group Director, Cadence and Ashutosh Majumdar, ARM
- Technical Papers
Days 2 and 3: System and Software Design Conference – October 31 and Novermber 1
- Cadence Booth #417
- Cadence System Development Suite
Discover how to reduce the efforts required in assembling and verifying digital SoCs while maximizing IP reuse. Significantly reduce design bring-up time, develop software faster and earlier, and speed verification. Cadence will demonstrate its System Development Suite including the Virtual System Platform and the Palladium Verification Computing Platform. You’ll see how our set of connected engines enable hardware/software co-development and verification from virtual prototyping through RTL simulation, acceleration, and emulation to FPGA-based prototyping. You’ll also see virtual prototyping of ARM big.LITTLE designs and a new development approach that combines the best of acceleration and emulation in a single runtime environment.
- Power-Aware Signal Integrity Analysis
ARM IP and processors are commonly found in high performing devices, from smartphones to server equipment. In all cases, high-performance and low-power requirements compete with the need to maintain reasonable costs. See the benefits of a system SI technology that allows power-aware signal integrity analysis using the most accurate interconnect models available for the chip, package, and board. Use the technology early in the design process to ensure a sound system architecture, and use it later in the design cycle as a signoff-level system simulator.
- Sponsored Session – Room #212; Wednesday, October 31, 11:30am – 12:30pm
- Prototyping and Early Software Development for ARM-Based Embedded Systems
- Design teams have many options for developing software early, including virtual prototyping, FPGA-based prototyping, acceleration, and emulation. This session will show you more about available prototyping options and how each can benefit your hardware and software teams. See solutions for overcoming challenges such as performance, accuracy, time of availability, development cost, replication cost, and connections to real-world interfaces. Discover the benefits of using a set of connected engines that enable hardware/software co-development and verification, from virtual prototyping through RTL simulation, acceleration, and emulation to FPGA-based prototyping. Compare the advantages of using the different engines individually vs. an approach where they are connected. Also see a detailed analysis of hybrid use models that combine RTL executed in emulation with transaction-level models running in virtual prototyping, connected through transactors, built from Accelerated Verification IP (AVIP).
- Technical Papers
Who should attend?Engineers, engineering managers, executives, and individuals using ARM processors
Questions About this Event?Send email to events@cadence.com
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