Low-Power Technology Summit
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Type: |
Cadence Event |
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Date: |
18 Oct 2012 |
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Location: |
Cadence Design Systems, Bldg. 10 Auditorium, San Jose, CA |
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Join us on October 18 for our Low-Power Technology Summit. Experts from Cadence and other leading companies will present the latest low-power design methodologies. Find out how they applied new techniques to meet their aggressive project goals.
The Summit is also a great opportunity to ask questions and network with industry experts. Whether your challenge is verification, physical implementation, or signoff, the Summit will give you a new perspective on improving your low-power flow and your overall productivity.
Agenda
| 08:30 |
Registration and Light Breakfast |
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| 09:15 |
Welcome and Opening Remarks |
Dr. Chi-Ping Hsu, Cadence |
| 09:30 |
Keynote Presentation |
Professor Jan Rabaey,
UC Berkeley |
| 10:30 |
Coffee Break |
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| 10:45 |
Low-Power Solution Technology Update |
Pete Hardee, Cadence |
| 11:30 |
Low-Power Design with ARM® Physical IP and POP™ IP |
Sathya Subramanian, ARM |
| 12:30 |
Lunch with R&D Roundtable |
Building 10 Cafeteria |
| 01:30 |
Low Power Verification in Mixed-Signal Designs
Cadence technology and customer experiences |
Shekar Chetput and
Luke Lang, Cadence |
| 02:15 |
Customer Case Study: Low-Power Design Experiences on Kinetis |
Anis Jarrar, Freescale |
| 03:00 |
Coffee Break |
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| 03:15 |
Power Formats: Standards & Support Update |
Dr. Qi Wang, Cadence |
| 03:45 |
Panel Discussion and Q&A |
Moderator: Richard Goering |
| 04:45 |
Prize Draw and Closing |
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| 05:00 |
Social Hour – Drinks and Canapés |
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Questions About this Event?
Send email to events@cadence.com