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TSMC Open Innovation Platform Ecosystem Forum

16 Oct 2012  
San Jose Convention Center, San Jose, CA  

20nm and Beyond: Leading the Way to Advanced Node Success

Cadence, through its work with TSMC as a leading member of the Open Innovation Platform® ecosystem, is leading the way to success at 20nm and beyond, and 3D-IC. See how at the sessions that Cadence is presenting at this year’s TSMC Open Innovation Platform Ecosystem Forum on Tuesday October 16 at the San Jose Convention Center.
Cadence Sessions
11:30 – 12:00 How to manage variability and double patterning at 20nm in custom design
2:00 – 2:30 3D-IC Silicon Interposer IC design flow using Cadence Encounter Digital Implementation (EDI) System
3:30 – 4:00 TSMC 20nm certification for Cadence 20nm RTL-to-GDSII flow
4:00 – 4:30 Enabling Design with Advanced Node Design IP for TSMC
5:00 – 5:30 Using latest-generation DDR4, LPDDR3 and Wide-IO DRAM devices with chips in TSMC's advanced 28nm and 20nm processes
A Platinum Sponsor of this year’s TSMC Open Innovation Platform Ecosystem Forum, Cadence is demonstrating leading technologies for realizing innovative designs with TSMC. Demonstrations include:
  • 3D-IC
  • 20nm Custom Design Enablement
  • AMS 3.0
  • High-performance/Advanced Node Digital Design
  • Design IP for DDR
  • Signoff
Visit Cadence at booth 414.
Find out more and register now!

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