20nm and Beyond: Leading the Way to Advanced Node Success
Cadence, through its work with TSMC as a leading member of the Open Innovation Platform® ecosystem, is leading the way to success at 20nm and beyond, and 3D-IC. See how at the sessions that Cadence is presenting at this year’s TSMC Open Innovation Platform Ecosystem Forum on Tuesday October 16 at the San Jose Convention Center.
Cadence Sessions11:30 – 12:00
How to manage variability and double patterning at 20nm in custom design2:00 – 2:30
3D-IC Silicon Interposer IC design flow using Cadence Encounter Digital Implementation (EDI) System3:30 – 4:00
TSMC 20nm certification for Cadence 20nm RTL-to-GDSII flow4:00 – 4:30
Enabling Design with Advanced Node Design IP for TSMC5:00 – 5:30
Using latest-generation DDR4, LPDDR3 and Wide-IO DRAM devices with chips in TSMC's advanced 28nm and 20nm processes
A Platinum Sponsor of this year’s TSMC Open Innovation Platform Ecosystem Forum, Cadence is demonstrating leading technologies for realizing innovative designs with TSMC. Demonstrations include:
- 20nm Custom Design Enablement
- AMS 3.0
- High-performance/Advanced Node Digital Design
- Design IP for DDR
Visit Cadence at booth 414.Find out more and register now!