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International Test Conference 2012

 
Type:
Industry Conference  
Date:
04 Nov 2012 - 09 Nov 2012  
Location:
Disney Hotel, Anaheim, CA  

Network with R&D Experts and Find Solutions for Your Test Challenges, Today

As a Silver Sponsor of ITC 2012, Cadence and our team of Encounter Test R&D experts will showcase our differentiated solutions for DFT, ATPG, and diagnostics. We invite you to meet with us and discuss how you can benefit from an integrated synthesis and test flow to help you realize your most challenging design at any technology node.

Please contact Lisa Jensen (ljensen@cadence.com) to arrange a private meeting time that fits your schedule between Tuesday, November 6 and Wednesday, November 7 from 9:00am–5:00pm.

Cadence Activities at ITC 2012

Poster presentation – session 12 – Wednesday 12:00pm – 2:00pm
Practical Approaches to ASIC Embedded Macro Test in an IEEE 1687 Environment
Presenters: K.Chakravadhanula, V. Chickermane, R. Khurana, C.P. Garg, Cadence Design Systems; C. Zoellin, B. Cowan, IBM

Technical paper – session 12.4 – Wednesday 2:00pm – 4:00pm
DFT Architecture and ATPG for Interconnect Test of JEDEC Wide-IO Memory-on-Logic Die Stacks
Presenters: B. Keller, V. Chickermane, S. Mukherjee, N. Sood, Cadence Design Systems; S.K. Goel, A. Mehta, F. Lee, TSMC; E. Marinissen, IMEC; S. Deutsch, Duke University

Panel 3 – Thursday 2:00 p.m. – 3:30 p.m.
Managing Process Variance in Analog Designs: Methods to manage the effect of process normal and process variance on analog circuit designs have driven significant invention within the analog design community.
Has test kept up with ensuring outgoing quality?
D. Floyd, Advantest (Moderator); E. Atwood, IBM (Organizer)
Panelists: D. O’Riordan, Cadence Design Systems; A. Frisch, Intel; G. Roberts, McGill University; S. Sunter, Mentor Graphics; M. Tirupattur, Analog Bits

Panel 5 – Thursday 2:00pm – 3:30pm
Testing High-Frequency and Low-Power Designs: Do the Standard Rules and Tools Apply Today's advanced designs are characterized by high frequency, low power, or both. Do we need to change our design practices and the tools which support them? DFT designers at the leading edge will challenge EDA vendors on the tools they need.
S. Davidson, Oracle (Moderator/Organizer)
Panelists: S. Banerjee, STMicroelectronics; J. Doege, AMD; H. Konuk, Broadcom; B. Keller, Cadence Design Systems; R. Press, Mentor Graphics


Additional Resources


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