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Archived Webinar: ACE Assertion-Based Dynamic, Formal, and Metric-Driven Verification Techniques with “ABVIP”

Original webinar date:
11 Dec 2012  
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To achieve first-pass success, the sophistication of ARM® ACE™-based designs must be matched by a comprehensive verification approach. This webinar will show how formal and assertion-based verification techniques, combined with assertion-based verification IP (ABVIP), can be used in concert with popular UVM testbench VIP. Specifically, in addition to leveraging hundreds of automatic protocol checks to quickly verify ACE functionality, the exhaustive formal analysis either classifies coverage holes as unreachable, or automatically provides the “missing” stimulus from the assertions to fill the holes and target specific scenarios. The results are automatically mapped back to a verification plan to update the project status. An industrial case study will be shown.

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