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Archived Webinar: SimVision Simplifies UVM SystemVerilog Macro Debug

 
Type:
Webinar  
Orignal webinar date:
27 Nov 2012  
Location:
Online  
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The SystemVerilog language allows users to significantly reduce the amount of code required within their environments through macro usage. This code reduction has traditionally come at a cost of reduced debug capabilities as well as making it more challenging for new engineers to debug the design more efficiently—until now. This webinar will introduce the latest in macro debug capabilities offered within the SimVision debug solution. Users of UVM-based environments, where macros are heavily utilized, will find this webinar particularly useful.

As we all know, debug is becoming a major bottleneck in verification. Design and verification engineers are looking for advanced debug capabilities to improve their overall verification productivity. Join this webinar to learn how new functionality in SimVision can help you reduce your debug time significantly.


Questions About this Event?
Send email to webinar_info@cadence.com

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