One of the primary goals of the UVM is to reduce the cost and burden of writing tests. This is accomplished by providing an abstract test definition interface in the form of sequences. Subsequently, much of the complexity involved with driving and monitoring the DUT is absorbed in UVM verification components (UVCs).
This webinar provides recommendations on how to create UVM sequences that can be leveraged by design engineers doing block-level testing through verification engineers who are developing complex verification environments.
For design engineers who may not be as familiar with SystemVerilog classes (or UVM), a step-by-step approach that makes sequences easier to code is the key value. For verification engineers responsible for both infrastructure (UVCs) and stimulus, sequences built for reuse and for runtime efficiency are critical to productivity.
Sequences are the means to inject stimulus into the DUT via the UVM environment. By design, the infrastructure for processing sequences, translating data from transactions to signals, monitoring, and more is all handled in a UVC. Consequently, the actual code of the sequence stays at an easy-to-grasp transaction level. In other words, sequences define how multiple transactions are used to form interesting stimulus. With the knowledge of how to code sequences in-hand, there are a few key concepts to ease debugging that each engineer should learn.
This webinar uses the UVM Reference Flow so that you can recreate everything you learn in your own environment.
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