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Archived Webinar: 5 Steps to Your First Power Shutoff (PSO) Verification

Orignal webinar date:
16 Oct 2012  
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Making the leap to your first power shutoff (PSO) circuit can be daunting. Do the isolation cells properly insulate the shutoff domain? Do the retention registers enable the SoC to return to full-power properly? Have enough tests been run to cover the power control module? Cadence has helped project teams answer these questions in hundreds of projects, enabling an approach that will lower the risks in your first project.

The 5 steps outlined in this webinar provide a proven approach that both reduces the effort to verify a PSO domain while also increasing the quality of the resulting design. It assumes a working knowledge of Verilog and/or VHDL and a basic knowledge of power formats. We’ll use the proven low-power capabilities in the Cadence® Incisive® Enterprise Simulator XL along with the Incisive Verification Kit examples>

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