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Archived Webinar: Is SystemVerilog the Future of Analog Modeling?

 
Type:
Webinar  
Orignal webinar date:
18 Sep 2012  
Location:
Online  
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More and more of today’s complex designs include analog functionality. As a result of the interactions and feedback loops between the digital and analog functionality, more verification of these interactions is needed at a functional level. However, because the simulation engines used for analog designs (Spice, FastSpice, etc.) run several orders of magnitude more slowly than a digital-only simulation, engineers turn to fast real-number models (RNMs) for simulating analog behavior in an accurate way for full-chip verification.

A significant speed-up in simulation performance can be achieved by replacing the analog portions of a design with functionally equivalent real-number models using real/wreal functionality in Verilog-AMS and/or SystemVerilog to achieve a 100–500x performance boost for top-level SoC verification.


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