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Archived Webinar: Why Debug at the Signal Level When SystemVerilog Class-Based Debug is So Simple?

Orignal webinar date:
21 Aug 2012  
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The SystemVerilog language allows users to model complex verification environments using sophisticated object-oriented programming (OOP) software techniques. Debugging within an OOP framework challenges previous HDL-only techniques, where dumping signals to waveforms and debugging post-process may have been the norm. This webinar will walk users through the advantages of using the debug power of SimVision within a complex class-based SystemVerilog environment for both interactive and post-process debug. We will focus mainly on UVM-based environments; however, non-UVM debug will also be addressed.

Questions About this Event?
Send email to webinar_info@cadence.com

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