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PCB West Conference 2012

Conference & Exhibition  
25 Sep 2012 - 27 Sep 2012  
Santa Clara, CA  

PCB West encompasses the entire PCB supply chain and brings together engineers, designers, fabricators, assemblers, and managers for a unique opportunity to improve skills, increase knowledge, and network with one another.

Visit Cadence in booth #206, where you’ll learn more about OrCAD apps and the latest developments in OrCAD / Allegro technologies. Our OrCAD and Allegro solutions help customers design mainstream and complex PCBs, quickly and cost-effectively.

Cadence is also part of the IPC-2581 consortium in booth #217, where we’ll demonstrate design data transfer between PCB EDA tool vendors and DFM/CAM vendors using IPC-2581. The consortium promotes the adoption of an open, neutral PCB design data transfer to manufacturing. It is open to any PCB design/supply chain company prepared to adopt the consortia’s objectives and commit to a roadmap for IPC-2581 adoption.

Be sure to attend one or more of the following Cadence speaking sessions:

Tuesday, Sept 25: 1:30 pm – 2:30 pm
Design Planning – A Common Sense Approach to Shortening Routing Time and Reducing Layers on PCBs
Speaker: Greg Horlick, Cadence

As a result considerable effort is invested in the exploration and physical implementation of designs that ultimately get restarted from scratch. This wasted effort results in higher product development costs that must be either passed on to the customer or absorbed as overhead. At the same time scarce manpower resources are utilized longer than necessary which can lead to missed market opportunities.

To combat these issues, companies (design teams) are looking for predictive methods to get a better "feel" for whether a design can be implemented at any time given the current state of the physical geometries and constraints. This predictive method or Design Planning can be used to get early feedback as to whether there is enough room to route a particular interface given the current geometric layout. This feedback can be used to make pin optimizations (using other CDN tools such as FSP), decisions regarding product form factor, component packing, cross-section, placement modifications and more. While it may seem inefficient to "Design Plan" as no actual routing is being done, this step actually saves time/money as it significantly reduces the "cost-ineffective" place/route/re-route scenario.

This paper will walk through a case study of a sample design and how to use Design Planning for reducing design cycle time allowing better utilization of existing resources and achieving the cost savings all companies are looking for. It will explore the concepts, how-to's and demonstrate the cost savings that can be realized by using Design Planning instead of "brute-force" methods.

Tuesday, Sept 25: 4:00 pm – 5:00 pm
PCB-Guided FPGA Pin Assignments
Speaker: Bruce Riggins, Cadence

The FPGA pin assignment process has typically been initiated by the FPGA designer; armed with FPGA-focused design tools and using their knowledge of the FPGA, logic, and timing requirements, FPGA designers will then tenaciously conjure up the pin assignments. But this forward-driven effort almost always results in a series of round-trips with the PCB designer to optimize those pin assignments so that they also work well for the PCB. The fundamental reason behind these iterations is conceptually easy to grasp but extremely difficult to resolve, either manually or algorithmically: FPGA tools do not comprehend the PCB (or even the most elementary details involved with PCB routing) and most PCB tools have roughly the same level of knowledge about the FPGA – none. In other words, neither designer has the information they need to do their job without constantly referring, and deferring, to the other.

But what if this common approach could be turned on its head? What if the PCB designer could be handed a rough set of FPGA pin assignments, and then, guided by intelligence from an FPGA-aware tool or algorithm, directly alter those pin assignments to accommodate the routing needs while concurrently adhering to the rules defined by the FPGA? He could then immediately influence the choice of pin assignments, early in the design cycle, and steer the FPGA designer, instead of the other way around.

This presentation discusses some of the latest ideas and developments in this area by first establishing the root of the problem and then highlighting how innovative new technologies and approaches are poised to help engineering teams reduce the (seemingly) endless FPGA-PCB pin assignment loop.

Wednesday, Sept 26: 2:30 pm – 3:30 pm
IPC-2581 Validation Test Program
Speaker: Ed Acheson, Cadence

The IPC-2581 standard provides a format that contains all data required to the manufacturing, assembly and test of printed circuit boards in a single file. A number of leading industry EDA vendors and manufacturers have teamed to validate the data generated by CAD tools through CAM and bare board fabrication. This session provides an update on their work.

Wednesday, Sept 26: 3:30 pm – 4:30 pm
Adoption Of IPC-2581 – An Update
Speakers: The IPC-2581 Consortium, Gary Carter – Fujitsu Networks, Hemant Shah – Cadence

Since the development of PCB CAD design tools more than 30 years ago, data to drive the manufacturing process has been driven by tool developers. Each tool developer provided their own format, with a portion of those becoming de facto standards. The IPC-2581 standard provides a format that contains all data required to the manufacturing, assembly and test of printed circuit boards in a single file. This standard, that is beginning to gain momentum in the industry, is independent of any tool manufacturing company, and is managed and controlled by an IPC committee made up of tool providers and ODMs dedicated to providing a complete and proper exchange of manufacturing data

The IPC-2581 Consortium is composed of representative from many different aspects of PCB design whose purpose is to drive the adoption of IPC-2581 in the industry. One of the roles of this consortium is to provide validation and prove the consistency of the IPC-2581 standard. Several test cases have been provided by design centers, which are used by the CAD and CAM tool vendors to compare the IPC-2581 data against Gerber, ODB++, NC Drill, etc. for accuracy and completeness. An aggressive schedule for validation of this data has been laid down, and results are posted on the consortiums web site.

Active participants in the drive to adopt IPC-2581 include CAD tool manufacturers Cadence Design Systems and Zuken, CAM tool providers Adiva, DownStream, and Wise, corporations such as Fujitsu Networks, Harris, and nVidia, and manufacturers such as Sanmina-SCI.

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