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Archived webinar - What is New in Encounter v11.1: High-Performance GHz+ Design

Original webinar date:
22 Mar 2012 9:00 AM  
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Attend this technical webinar and find out the latest Cadence Logic Design and Encounter Digital Implementation (EDI) System has to offer in enabling high-performance GHz and low-power microprocessor-based SoCs.

Meet your power, performance, and area targets with physical synthesis and physical implementation technologies such as our GigaOpt optimization engine and clock concurrent optimization (CCOpt). CCOpt users are realizing up to 10% boosts in timing closure and up to 30% improvements in power and area. Enhance your productivity, time to market, and competitive advantage. Attend this webinar and find out how to enable your next SoC with Cadence technologies.

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