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Archived Webinar: Connecting SystemVerilog Real Numbers and Verilog-AMS Nets

Orignal webinar date:
09 May 2012  
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This webinar will discuss the connection between these domains and how this enables analog block integration regardless of abstraction level (SPICE, AMS models, real number models). We will also discuss how to add to your verification quality and productivity using a metric-driven approach, which is enabled by this connection.

Questions About this Event?
Send email to webinar_info@cadence.com

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