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DVCon 2012

Industry Conference  
27 Feb 2012 - 02 Mar 2012  
DoubleTree Hotel, San Jose, CA  

DVCon is the premier conference for chip and system design and functional verification, focused on bringing information from the leading edge of technology, techniques, standards, and methods to the user community.

Visit Cadence in booth #1102 and talk to one of our technical experts about how to address your toughest functional verification challenges. Watch one of our demos on:
  • Low-power verification with UVM SystemVerilog
  • Simplified coverage visualization and management
  • Verification IP
  • FPGA-based prototyping
  • A new formal verification "app" to reach coverage closure
You can also hear about Cadence solutions at one of our many conference activities:

Accellera-Sponsored Tutorials Tuesday Lunch Tutorial: Earn Your Degree in the Low-Power Arts and Sciences

Panel: Build or Buy: Which is the Best Practice for Hardware-Assisted Verification?

Conference Papers: Tuesday, February 28
  • 131-WH864: The Case for Low-Power Simulation-to-Implementation Equivalence Checking (Cadence)
  • 131-TO356: Register This! Experiences Applying UVM Registers (Cadence)
  • 131-PD272: Hardware/Software Co-Verification using Specman and SystemC with TLM Ports (PMC-Sierra)
  • 131-ZS887: Yikes! Why is My SystemVerilog Testbench So Slooooow? (Cadence with IBM)
  • 131-HW244: Shaping Formal Traces without Constraints: A Case Study in Closing Code Coverage on a Crypto Engine using Formal Verification (Ubicorn)
  • 131-VI576: From Spec to Verification Closure: A Case Study of Applying UVM-MS for First-Pass Success to a Complex Mixed-Signal SoC Design (Maxim)
Conference Papers: Wednesday, February 29
  • 131-UE177: Memory Debugging of Virtual Platforms with TLM 2.0 (Cadence)
  • 131-CS172: Bringing Continuous Domain into SystemVerilog Covergroups (Cadence)

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