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Allegro and OrCAD User Papers, Roadmaps, and Techtorials at CDNLive! Silicon Valley

 
Type:
CDNLive!  
Date:
13 Mar 2012 - 15 Mar 2012  
Location:
DoubleTree hotel and Cadence campus, San Jose, CA  

Join us for CDNLive! Silicon Valley 2012 at the DoubleTree Hotel on March 13-14. Network with Cadence® technical staff and listen to user papers on Allegro® and OrCAD® technologies.

This year, we have extended CDNLive! with a free one-day event specifically for PCB and IC packaging designers. On March 15 at the Cadence campus, you can meet with our experts to get the latest and greatest details on Allegro/OrCAD technology. Attend any of the roadmap sessions that interest you. Don’t miss the lively roundtable discussion where you can ask Cadence PCB and IC Packaging R&D any question you may have about Allegro/OrCAD technology. After lunch, choose to participate in either the hands-on Design Planning Techtorial or the Basic SI Primer. The complete agenda for March 15th is included below

You must register for one or both of these events.

Allegro/OrCAD Roadmaps and Techtorials – March 15, 2012 (Cadence Campus)
March 15 Agenda Presenter(s)
8:00am Registration
8:30-8:45am Welcome address AJ Incorvaia, VP Engineering for PCB & IC Packaging Products
8:45-9:30am Design authoring roadmap Hemant Shah, Product Marketing Director, Allegro PCB Products
9:30-10:15am PCB layout and routing roadmap Hemant Shah, Product Marketing Director, Allegro PCB Products
10:15-10:30am Break
10:30-11:00am SI roadmap Brad Griffin, Product Marketing Director, Allegro PCB Products

11:00-11:30am ICP roadmap Brad Griffin, Product Marketing Director, Allegro PCB Products
11:30am-12 noon Roundtable Senior Engineering Directors and Architects for PCB and IC Packaging Products
12 noon-1:00pm Lunch with R&D and Product Engineering leads
1:00-5:00pm Design Planning Techtorial Robert Jardon, Senior PCB Designer at FreedomCAD, will share his successes in using the Allegro PCB Designer Flow Planner, followed by a hands-on techtorial on Design Planning to shorten routing time and reduce layers
1:00-5:00pm Basic SI Primer Terry Jernberg, Principal Product Engineer at Cadence, will teach the basics of transmission line theory, terminations, crosstalk, and PCB stack-up design, emphasizing how PCB designers can make decisions during the layout process

PCB and IC Packaging User Papers – March 14, 2012 (DoubleTree Hotel, San Jose)

  • 9:00am:
    A Comprehensive Analysis and Verification Methodology for DDR3 Interfaces
    Jerry Long, EMA, discusses how Allegro PCB SI and TimingDesigner® work together to achieve timing closure on DDR3 memory subsystems
  • 10:00am:
    Accelerating the Methodology of PCB PDN Design and Analysis
    Dennis Nagle, Cadence, will update you on the latest PDN analysis technology introduced in 16.5
  • 11:00am:
    PCB and Package Co-Design Using 3D EM full-wave simulation
    Antonio Ciccomancini, CST, updates you on Microwave Studio integration with Cadence PCB and IC packaging products
  • 1:30pm:
    Why Doesn’t My Board Work?
    James Hixson, ADIVA, presents a methodology to discover hidden design flaws to ensure the board you send to your fabricator will work the first time
  • 2:30pm:
    The 21st Century Approach to Transferring Design Data to Manufacturing
    Gary Carter, Fujitsu Networks Communications, will update you on IPC-2581 to streamline design data transfer to manufacturing
  • 2:30pm:
    Multi-Chip Module (MCM) Package Design Flow Using Cadence SiP Design Tools and Agilent Package Analysis
    Sufia Salim, Analog Devices, discusses how Cadence SiP tools integrated with Cadence Virtuoso and ADS were used for cell phone towers and base station products
  • 3:45pm:
    Creating Apps for OrCAD Capture: Experiences, Tips, and Examples
    Nikhil Punnakkali, EMA Design Automation, discusses lessons learned on creating apps (for Capture and PCB Editor) for the OrCAD Capture Marketplace
  • 3:45pm:
    Using Co-Design to Optimize System Interconnect Paths
    Broadcom and Cadence co-present how Broadcom used a single canvas co-design methodology to shorten their design cycle
  • 4:45pm:
    Improving IDF Geometry Definitions
    Ron Dallas, Teradyne, discusses the creation of a new sub-class for IDF geometry for your PCB library
  • 4:45pm:
    Silicon-Package-Board Co-Design and Co-Analysis for a High-Performance Multi-Core Chip
    Tilera, Bayside Design, and Cadence co-present a new methodology to optimize and analyze chip-package-board using a single canvas
Register for CDNLive! Silicon Valley, March 13-14

Register for the CDNLive! Allegro/OrCAD Event, March 15


Questions About this Event?
Send email to events@cadence.com