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EDA360 Silicon Realization Technology on Tour – Logic Design Event

 
Type:
Seminar  
Date:
27 Feb 2012 (9.00am – 5.00pm)  
Location:
Tel Aviv, Israel  

Learn, Share Ideas and Network with Cadence Logic Design Users and R&D Experts

Date: February 27, 2012
Venue: Cadence Design Systems
6 Hahoshlim St.
Herzelia 46140 Israel
Time: 9.00am – 5.00pm

Find out how other logic designers are reaching their goals by leveraging Cadence® Silicon Realization technologies that go beyond traditional synthesis. Hear from Cadence R&D on a wide range of topics: physically-aware synthesis, low-power synthesis, integrated test, constraint management, hierarchical design, prototyping, auto-handling of ECOs, advanced ECO logic optimization, low-power equivalence checking, and transistor-level verification coverage.

If you use Encounter® RTL Compiler, the Conformal® product family, or Encounter Test, this is a must-attend event. You’ll learn best practices and new techniques to help you: close on multiple design goals in parallel, estimate RTL power, achieve your performance and area targets post-synthesis with results that still correlate post-implementation, navigate the complexities of low-power design, minimize congestion, insert DFT infrastructure, check logical equivalency, and implement ECOs in your SoC.

Space is limited. Register now »

Agenda
08:30-09:30 REGISTRATION and COFFEE
09:30-09:45 Welcome address
09:45-10:45 RTL Compiler and DFT: Enhanced Global Synthesis for Concurrent PPA Optimization and Single-Pass Synthesis and Test Insertion
10:45-11:30 RTL Compiler Physical: Physically-Aware Synthesis for Complex, High Performance Designs
11:30-11:45 COFFEE
11:45-12:45 Conformal ECO Designer: Smarter Auto-Handling of ECOs in Hierarchical Designs and Advanced ECO Logic Optimization
12:45-13:30 LUNCH
13:30-14:15 Conformal LEC: Optimize Turnaround Time through New RC-LEC Framework, Synthesis Guidance, and New Web Interface
14:15-15:00 Conformal Constraint Designer: Increase User Productivity with New TCL Mode and Addition of Clock Domain Crossing Functional Checks
15:00-16:00 Conformal Low Power: Expanding Capabilities with Low Power Equivalence Checking and Transistor-Level Verification Coverage
16:00-17:00 Rapid Adoption Kit Demos and COFFEE
17:00 FINISH

Questions About this Event?
Send email to marketing_euro@cadence.com