Learn, Share Ideas and Network with Cadence Logic Design Users and R&D Experts
||February 27, 2012|
||Cadence Design Systems|
6 Hahoshlim St.
Herzelia 46140 Israel
||9.00am – 5.00pm|
Find out how other logic designers are reaching their goals by leveraging Cadence® Silicon Realization technologies that go beyond traditional synthesis. Hear from Cadence R&D on a wide range of topics: physically-aware synthesis, low-power synthesis, integrated test, constraint management, hierarchical design, prototyping, auto-handling of ECOs, advanced ECO logic optimization, low-power equivalence checking, and transistor-level verification coverage.
If you use Encounter® RTL Compiler, the Conformal® product family, or Encounter Test, this is a must-attend event. You’ll learn best practices and new techniques to help you: close on multiple design goals in parallel, estimate RTL power, achieve your performance and area targets post-synthesis with results that still correlate post-implementation, navigate the complexities of low-power design, minimize congestion, insert DFT infrastructure, check logical equivalency, and implement ECOs in your SoC.
Space is limited. Register now »
||REGISTRATION and COFFEE |
||Welcome address |
||RTL Compiler and DFT: Enhanced Global Synthesis for Concurrent PPA Optimization and Single-Pass Synthesis and Test Insertion |
||RTL Compiler Physical: Physically-Aware Synthesis for Complex, High Performance Designs |
||Conformal ECO Designer: Smarter Auto-Handling of ECOs in Hierarchical Designs and Advanced ECO Logic Optimization|
||Conformal LEC: Optimize Turnaround Time through New RC-LEC Framework, Synthesis Guidance, and New Web Interface |
||Conformal Constraint Designer: Increase User Productivity with New TCL Mode and Addition of Clock Domain Crossing Functional Checks|
||Conformal Low Power: Expanding Capabilities with Low Power Equivalence Checking and Transistor-Level Verification Coverage |
||Rapid Adoption Kit Demos and COFFEE |
Questions About this Event?Send email to email@example.com