Archived webinar - TSMC-Cadence DFM Services for 40-28nm
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Type: |
Webinar |
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Orignal webinar date: |
05 Dec 2011 |
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Location: |
Online |
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Collaboration Enables Turnkey Services for Advanced-Node Lithography and CMP Hotspot Analysis.
Silicon variability impacts both the physical integrity and the parametric performance of a design. Cadence and TSMC have collaborated to deliver best-in-class DFM services that include model-based simulation of LPC and CMP verification for 40-28nm. Using these turnkey services, design teams can detect litho or CMP hotspots and fix them during the IC design phase—prior to tapeout. Unlike the traditional method of buying EDA tools to perform DFM checks, Cadence DFM Services offer flexibility for design teams who desire the fastest knowledge ramp time, minimal tool learning, no IT burden, and zero CPUs to run the jobs. Cadence provides comprehensive reports with hotspot location, layout fixing guidelines, and the output files that enable automatic fixing in digital implementation and custom design flows.
In this joint TSMC-Cadence webinar, you'll find out what, when, why, and how designer cans incorporate DFM Services into an existing 40nm or 28nm design flow. Please send any questions to
dfmservices@cadence.com.
Questions About this Event?
Send email to webinar_info@cadence.com
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