The advent of IP-based and SoC designs have introduced new levels of complexity to the IC development process. Disparate design teams, a multitude of design data from a variety of sources, and constantly changing design requirements all result in what can sometimes be a very chaotic process. Engineering teams and management need an efficient and intuitive foundation to work from to deal with the breadth and depth of design data involved in IC design. And since the data can come in from R&D centers around the world, the data must be carefully managed during the entire design cycle to prevent costly last-minute errors.
This webinar will demonstrate how Methodics VersIC, ProjectIC, and BuildIC products can be used within the Cadence® Virtuoso® custom/analog flow, as well as with Verilog and VHDL-based designs, to ensure higher quality and productivity. Topics covered include constraint design, testbench management, documentation, version control, configuration management, data management and distribution to remote sites, and access control.
In addition, a new SoC development platform from Methodics will be introduced. ProjectIC is the SoC portal that enables designers to track which versions of which IP are being used in which projects across geographically remote sites. In addition, design metadata such as power consumption, test coverage, and other important metrics can be harvested from a user’s design environment to manage IP quality and important operating characteristics.
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